1. Field of the Invention
The present invention relates generally to a system and method for consolidating separate initialization EEPROMs from various integrated components on a circuit board into a single EEPROM module. More particularly, the present invention relates to an EEPROM module that may include an arbiter and protocol translator configured to allow a shared EEPROM to appear as a dedicated EEPROM to more than one component.
2. Background of the Invention
Early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components were typically coupled together using a network of address, data and control lines, commonly referred to as a "bus." As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or by attaching the peripheral devices to sockets on the main system circuit board (or "motherboard") which were connected to the system bus. One early bus that still is in use today is the Industry Standard Architecture (ISA) bus. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with most computer systems. The ISA bus includes 16 data lines and 24 address lines and operates at a clock speed of 8 MHz. A large number of peripheral components have been developed over the years to operate with the ISA protocol.
The components which connect to a given bus receive data from the other components on the same bus via the bus signal lines. Selected components may operate as "bus masters" to initiate data transfers over the bus. Each component on the bus circuit operates according to a bus protocol that defines the purpose of each bus signal and regulates such parameters as bus speed and arbitration between components requesting bus mastership. A bus protocol also determines the proper sequence of bus signals for transferring data over the bus. As computer systems have continued to evolve, new bus circuits offering heightened functionality have replaced older bus circuits, allowing existing components to transfer data more effectively.
One way in which the system bus has been made more effective is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, a new bus architecture called Extended Industrial Standard Architecture (EISA) was developed. The EISA bus protocol permits system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus independently of the CPU. Another bus that has become increasingly popular is the Peripheral Component Interconnect (PCI) bus. Like the EISA bus, the PCI bus provides bus master capabilities to devices connected to the PCI bus. The PCI bus operates at clock speeds of 33 MHz or faster. Current designs contemplate implementing a 100 MHz PCI bus.
To ensure that existing components continue to remain compatible with future generations of computer systems, new computer designs often include many different types of buses. Because different buses operate according to different protocols, bridge devices are used to interface, or bridge, the different buses. Such a scheme permits components coupled to one bus to exchange data with components coupled to another bus.
FIG. 1 illustrates an example of a configuration of various computer components that may be found in a representative prior art computer system. The computer system of FIG. 1 includes a CPU 102 coupled to a bridge logic device 106 via a CPU bus. The bridge logic device 106 is sometimes referred to as a "North bridge" for no other reason than it often is depicted near the top of a computer system drawing. The North bridge 106 also couples to a main memory array 104 by a memory bus, and may further couple to a graphics controller 108 via an accelerated graphics port (AGP) bus. The North bridge 106 couples CPU 102, memory 104, and graphics controller 108 to the other peripheral devices in the system through a primary expansion bus (BUS A) such as a PCI bus or an EISA bus. Various components that understand the bus protocol of BUS A may reside on this bus, such as an audio device 114, an external bus adapter (e.g. an IEEE 1394 interface device) 116, and a network interface card (NIC) 118. These components may be integrated onto the motherboard, as suggested by FIG. 1, or they may be plugged into expansion slots 110 that are connected to BUS A. As technology evolves and higher-performance systems are increasingly sought, there is a greater tendency to integrate many of the devices into the motherboard which were previously separate plug-in components.
If other secondary expansion buses are provided in the computer system, as is typically the case, another bridge logic device 112 is used to couple the primary expansion bus (BUS A) to the secondary expansion bus (BUS B). This bridge logic 112 is sometimes referred to as a "South bridge" reflecting its location vis-a-vis the North bridge 106 in a typical computer system drawing. An example of such bridge logic is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation. Various components that understand the bus protocol of BUS B may reside on this bus, such as hard disk controller 122, Flash ROM 124, and Super I/O (input/output) controller 126. Slots 120 may also be provided for plug-in components that comply with the protocol of BUS B.
The Super I/O controller 126 typically interfaces to basic input/output devices such as a keyboard 130, a mouse 132, a floppy disk drive 128, a parallel port, a serial port, and sometimes various other input switches such as a power switch and a suspend switch. The Super I/O controller 126 often has the capability to handle power management functions such as reducing or terminating power to components such as the floppy drive 130, and blocking the clock signals that drive components such as the bridge devices 106, 112 thereby inducing a sleep mode in the expansion buses. The Super I/O controller 126 may further assert System Management Interrupt (SMI) signals to various devices such as the CPU 102 and North bridge 106 to indicate special conditions pertaining to input/output activities such as sleep mode. The Super I/O controller 126 may incorporate a counter or a Real Time Clock (RTC) to track the activities of certain components such as the hard disk 122 and the primary expansion bus, inducing a sleep mode or reduced power mode after a predetermined time of inactivity. The Super I/O controller 126 may also induce a low-power suspend mode if the suspend switch is pressed, in which the power is completely shut off to all but a few selected devices. Exempted devices might be the Super I/O controller 126 itself and NIC 118.
Many of the peripheral components may include a programmable read-only memory (PROM) of some form for initializing configuration registers and providing serial numbers or unique identifiers of one form or another. This technique is popular because the use of PROMs to store device settings advantageously reduces the number of components and reduces design effort. Some bus protocols, such as PCI, require that components be provided with configuration information including a vendor id, a serial number, perhaps a subsystem vendor id, revision numbers, and the like. Typically, PCI peripherals will retrieve this information from the PROMs at power-up and store it in internal configuration registers reserved for this purpose. Electrically erasable PROMs (EEPROMs) are often used with configurable peripheral components since they allow a device's configuration information to be modified and retained indefinitely. Examples of components which would likely include an EEPROM are graphics accelerators, audio devices, NICs, modems, and external bus interfaces (e.g. IEEE 1394, SCSI).
Most EEPROMs have a capacity of at least 128 bytes and support a serial interface such as the Inter IC bus (I.sup.2 C), Microwire.TM. bus or the Serial Peripheral Interface (SPI). Normally, less than 1/3to 1/2of the full storage capacity of these EEPROMs is used, and in most cases these EEPROMs are only used during the device's initialization phase (i.e. during power-up). This results in numerous EEPROMs each having excess capacity when peripheral components are integrated onto the motherboard. It would be desirable to have a shared, central EEPROM module that appears as an individual dedicated EEPROM to each of several components in the system, thus minimizing the number of components required on the system board.